Contact LogicVisionSite Map
LogicVision SolutionsLogicVision ProductsCompanyLogicVision SupportInvestorsLogicVision News and Events

ScanBurst


View Product
Presentation

(Load Time = :30 to 1:00
depending on connection)

Datasheet

Technical Backgrounder

ScanBurst is an at-speed design for test (DFT) tool, designed to overcome the limitations of traditional at-speed DFT techniques. ScanBurst has been specifically engineered for full integration with Mentor Graphics' automatic test pattern generation (ATPG) products, TestKompress™ and FastScan™, offering at-speed single-capture test application and support for hierarchical test generation and application.

ScanBurst and Mentor's automatic test pattern generation (ATPG) products, TestKompress™ and FastScan™, together provide a fully integrated at-speed test solution for nanometer SoC designs.  

The traditional approach of testing for performance related defects with ATPG-based solutions has been to generate patterns that target transition delay faults. These patterns are applied using two at-speed functional clock cycles to create a "launch" and "capture" sequence. Unfortunately, this technique often lacks accuracy, resulting in test escapes or yield loss.   ScanBurst addresses these problems by providing an environment to easily insert scan and clock control structures for at-speed testing based on LogicVision's patented BurstMode Timing technology. BurstMode Timing provides accurate at-speed test under conditions that reflect the functional operation mode.

ScanBurst supports a hierarchical architecture to scale with design size, speed, and power. The ScanBurst architecture efficiently isolates each core during test application. This patented core isolation technique separates the design into independent core components, with minimal area overhead and no impact on performance. A hierarchical test flow is crucial in managing lower power designs, as average power consumption during scan testing is generally much higher than during functional operation. In addition, test pattern generation times are reduced as individual cores in isolation need only be considered by FastScan or TestKompress, and test patterns can be reused on duplicate cores within a design. This also results in a reduced test pattern volume.

The ScanBurst infrastructure is added to a design using LogicVision's LV2005 automation flow. This fully hierarchical flow ensures limited impact to the design schedule and quick turn-around time. The LV2005 flow also automatically creates all necessary procedural files and invocation scripts for FastScan and TestKompress, greatly simplifying the test pattern generation process.