ETLogic Embedded Logic Test
ETLogic is industry-proven embedded test and measurement IP, and corresponding design automation software, for the at-speed test and diagnosis of digital logic blocks. This product's random-pattern-based approach provides the most efficient trade-off between test time and test quality. A hierarchical option to ETLogic delivers a capability that is unparalleled in features and benefits for creating testable, hierarchically-defined digital logic cores that are ready for assembly. This hierarchical capability enables designers to implement logic test in the same hierarchical flow used for the functional design and, consequently, allows the assembly of multi-million-gate SoCs in a block-level divide and conquer approach.
The ETLogic patent pending BurstMode test-timing architecture provides at-speed test application, regardless of the number of clock domains or frequencies. It does not suffer the test time and diagnostic drawbacks of competing double-capture test-timing approaches.
The ETLogic approach enables the application of a very large number of random patterns in a limited amount of test time. This cost effectively provides high stuck-at and transition fault coverages as well as very high N-detect counts. The N-detect count measures the number of times each fault in a circuit is detected by a different test pattern and is a direct measure of overall defect coverage
These industry leading benefits are achievable with minimal design effort. The ETLogic IP is added to a design using LogicVision's advanced LV2005™ automation flow at either the RTL or Gate level This fully hierarchical flow ensures limited impact to the design schedule and quick turn-around time. The LV2005 flow is also tightly integrated to all major 3rd party physical design flows including RTL-to-GDSII flows and has no impact to design performance.
The output of the embedded test automation flow is a fully verified netlist containing all of the embedded test IP and infrastructure. The result is a fully verified test capability that ensures immediate bring-up of first silicon.
Hierarchical ETLogic Option
Hierarchical ETLogic supports the addition of ETLogic controllers to logic blocks at any level of the ASIC/SoC design. The ETL controller associated with each treated block supports both random pattern testing as well as external scan test.
Hierarchical ETLogic provides unique mechanisms to isolate blocks for multi-clock-domain, at-speed test, including control options to allow testing of any number of modules in parallel, and clock management to control clocking to blocks not being tested for power saving objectives.
Two forms of logic core isolation are provided with Hierarchical ETLogic: dedicated isolation and shared isolation. The dedicated isolation approach supports the requirements of the IEEE 1500 standard for test-ready cores. LogicVision's patented shared isolation approach minimizes performance and area impact through the re-use of functional flip-flops.
Access to the various ETLogic controllers is provided through a hierarchical TAP architecture compliant with the IEEE 1500 standard. Lower level TAPs (called WTAPs) added to each core result in a fixed test interface that supports any number of embedded test controllers. The advantages of this approach are highly reduced global test signal routing as well as incremental assembly and verification.
ETLogic Compression Option
LogicVision's Compression option to ETLogic builds upon the embedded logic test capabilities to also provide support for ATPG compression. The solution can be used stand-alone or in conjunction with the ETLogic random pattern test capabilities.
The ETLogic compression option typically provides 100X reductions in both test time and test data volume over standard ATPG. Compressed patterns can be applied using LogicVision's BurstMode at-speed timing architecture. Advantages of using BurstMode over competitive double-capture timing approaches include higher transition fault coverage numbers, lower pattern counts, and greater diagnosability.
